Tag Archives: hardware

CLasH: Haskell to VHDL compiler in AUR

CLaSH is a tool-chain/language to translate subsets of Haskell to synthesizable VHDL. Haskell modules (example) written in a hardware-oriented subset of Haskell are translated into VHDL by the library. That is, you can design hardware directly in Haskell, and generate hardware designs from GHCi.

The Hackage package is now available in AUR.

Amongst other things, it provides a “:vhdl” extension to the GHCi command line, allowing you to generate hardware designs from the GHCi prompt. For more information about CLaSH, see the examples, sources and documentation project page, and the demo from the Haskell Workshop last year:

Other hardware-related libraries in Haskell in AUR:

  • chalmers-lava2000 library: Hardware description library
  • clash library: CAES Language for Synchronous Hardware (CLaSH)
  • ForSyDe library: ForSyDe’s Haskell-embedded Domain Specific Language.
  • Wired library: Wire-aware hardware description
  • york-lava library: A library for digital circuit description.