CLasH: Haskell to VHDL compiler in AUR

CLaSH is a tool-chain/language to translate subsets of Haskell to synthesizable VHDL. Haskell modules (example) written in a hardware-oriented subset of Haskell are translated into VHDL by the library. That is, you can design hardware directly in Haskell, and generate hardware designs from GHCi.

The Hackage package is now available in AUR.

Amongst other things, it provides a “:vhdl” extension to the GHCi command line, allowing you to generate hardware designs from the GHCi prompt. For more information about CLaSH, see the examples, sources and documentation project page, and the demo from the Haskell Workshop last year:

Other hardware-related libraries in Haskell in AUR:

  • chalmers-lava2000 library: Hardware description library
  • clash library: CAES Language for Synchronous Hardware (CLaSH)
  • ForSyDe library: ForSyDe’s Haskell-embedded Domain Specific Language.
  • Wired library: Wire-aware hardware description
  • york-lava library: A library for digital circuit description.

2 responses to “CLasH: Haskell to VHDL compiler in AUR

  1. Good Job! I am also a researcher in the field of High-Level Synthesis (compiling high-level languages into low level languages such as verilog or VHDL).

    The biggest challenge in high-level synthesis is exposing parallelism. Converting any software to a simple state machine is trivial. Synthesizing programs which are partially parallel is more difficult. I wonder what is it about Haskel that makes it an ideal candidate for this.


    • A colleague stumbled upon this blog while google’ing, so sorry for the late reply.

      The basic premise why using functional languages (like Haskell) to describe hardware is a good idea is the following:
      – Combinational hardware can be directly described by a mathematical model/equation.
      – Functional languages are very good as (de-)composing mathematical functions.

      What is also important is that the order in which a functional language is evaluated does not matter as long as data-dependencies are respected. This means we can very directly translate a Haskell function into a set of concurrent VHDL statements; and as a result that everything that can be executed in parallel will happen in parallel on the hardware. We translate then translate function applications to component instantiations, which again exploits all the parallelism that is available in the original Haskell description. More elaborate explanations can be found in the published papers and the master theses of me and Matthijs (all found on the clash website).


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